This application claims priority from Korean Priority Document No. 01-9606, filed on Feb. 26, 2001 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to semiconductor memory device, and more particularly, to an input-output line sense amplifier of a semiconductor memory device.
2. Description of the Related Art
Referring to FIG. 1, a memory cell array 11 is a semiconductor memory device that includes a memory cell 111. In a data read operation, predetermined data stored in memory cell 111 are amplified through a pair of bit lines BL and BLB by a bit line sense amplifier 112. An amplified signal is transmitted through column selecting transistors 113 and 114 to a pair of local input-output lines IO and IOB and a pair of global input-output lines DIO and DIOB. Data of the global input-output lines DIO and DIOB are amplified by an input-output line sense amplifier (IOSA) 13 and then is output to the outside via an output buffer 15 and an output pin DQ.
In the prior art it has been difficult to make the input-output line sense amplifier 13. In general, the options are to make it either as a current sense amplifier or a voltage sense amplifier.
The problem is that, when reading data, there is little difference between voltages of the input-output line DIO and DIOB. Thus, there is a very small difference to detect. Accordingly, the current sensing amplifier is widely preferred, since its sensing and amplifying speeds are faster than that of the voltage sense amplifier. But that is not enough, either. Since the output signal of a current sense amplifier has low voltage level, a voltage sense amplifier is then added afterwards to convert it to a CMOS level. But including the voltage sense amplifier decreases the overall sensing and amplifying speeds.
Referring to FIG. 2, a prior art implementation is shown for the input-output line sense amplifier 13. In the input-output line sense amplifier (IOSA) 13, a signal output from a current sense amplifier (CSA) 131 is amplified by a voltage sense amplifier (VSA) 132 and then is input into a latch 133. The latch 133 transforms the signal amplified by the voltage sense amplifier (VSA) 132 to a CMOS level.
FIG. 3 is a circuit diagram of the current sense amplifier (CSA) 131 shown in FIG. 2. Here, Mp11 and Mp12 represent PMOS transistors, and Mn11, Mn12, and Mn13 represent NMOS transistors. DIO and DIOB represent a pair of input-output lines, and EN represents an enabling signal.
FIG. 4 is a circuit diagram of the voltage sense amplifier (VSA) 132 shown in FIG. 2. Referring to FIG. 4, the voltage sense amplifier (VSA) 132 has the structure of a differential amplifier. Here, Mp31 through Mp34 represent PMOS transistors and Mn31 through Mn35 represent NMOS transistors. O1 and O1B represent a pair of output signals output from the current sense amplifier (CSA) 131, and EN represents an enabling signal.
FIG. 5 is a circuit diagram of the latch 133 shown in FIG. 2. Here, Mp41 through Mp44 represent PMOS transistors, and Mn41 through Mn43 represent NMOS transistors. O2 and O2B represent a pair of output signals of the voltage sense amplifier (VSA) 132, and LAT represents a latch enabling signal. DOUT and DOUTB represent a pair of output signals output from the latch 133 of the input-output line sense amplifier (IOSA) 13 shown in FIG. 2.
The conventionally made input-output line sense amplifier (IOSA) 13 described above consumes a large amount of current, which is undesirable. Worse, it includes the voltage sense amplifier (VSA) 132 having the structure of a differential amplifier, thus increasing direct current (DC) voltage.
The invention provides an input-output line sense amplifier of a semiconductor memory device, which senses an input-output line and a complementary input-output line transmitting data read from a memory cell.
The device of the invention includes a current sensing circuit for sensing a first portion of the signal current and a first portion of the complementary current. It also includes a first amplifier operating from a second portion of the signal current and a second portion of the complementary current to generate an output signal from a first detected output of the current sensing circuit, and a second amplifier operating from a third portion of the signal current and a third portion of the complementary current to generate an output signal from a second detected output of the current sensing circuit. A latch receives the output signals generated by the first and second amplifiers.
Preferably the second portion of the signal current corresponds to an equal fraction of the signal current as the second portion of the complementary current.
The input-output line sense amplifier does not include a voltage sense amplifier having the structure of a differential amplifier, and thus it consumes only a small amount of current and direct current (DC) compared to the prior art.